MIDAS-M UHF Radar Receiver Hardware
The UHF Radar Receiver hardware design is implemented as cPCI board with two tuner sections, a coherence and trigger input interface, a Microtronix Firefly FPGA module, 100 Mbit Ethernet, RS232 serial via USB, and power via the cPCI backplane connector. Dual RF inputs and a single PLL are provided for each tuner section. Tuners and PLLs are digitally controlled from the FPGA module. This module implements a firmware NIOS II CPU which runs the ucLinux operating system.
Board Design Overview
The circuit board is divided into sections and fabricated using six layers of FR-4 to provide for internal power and ground planes. RF lines are run internally over long paths using stripline to improve isolation. Tuners are modular and shielded with external power and Synergy microwave PLLs. Inputs and outputs for RF signals lie on the card edge of the tuner and use SMA connectors. External 10 MHz and PPS reference line inputs are provided along with an external trigger input. The 10 MHz reference is expected to be a sine wave in the +10 dBm range. This signal is split and input to the PLLs and also converted to a digital signal for precise timing in the FPGA. Control signals are level translated and driven by an Altera Cyclone FPGA which is provided by a Microtronix Firefly module. Ethernet and serial to USB communications are provided along with a JTAG programming interface. Reconfiguration and reset switches are also provided.
Microtronix Firefly
The Microtronix Firefly module combines an Altera Cyclone 1C12 FPGA with 16 MB SDRAM and 8 MB Flash memory in a form factor interfaced using four 100 mil pin headers. This module is highly integrated and saved some development risk and time. Newer versions of the module are not compatible with the tool set needed for ucLinux but that may evolve in the future. It is possible to simply integrate the equivalent circuitry if necessary.
The LED on the Firefly module is used to indicate lock of the onboard FPGA PLL to the 25 MHz input clock. This PLL generates the 75 MHz system clock.
The NIOS II processor on the Firefly is clocked at 75 MHz (13.3 nsec) and this oscillator time sets the lowest synchronous response time of the hardware.
Analog Tuner Overview
The analog tuner consists of two RF inputs, an RF output, and an external LO input. The tuner provides a single conversion down-converter with an IF output of 126 MHz. An RF switch at the input can select either input, bypass the down-converter, select a noise diode, or provide a 50 ohm terminator. The LO can be blanked, select from the internal PLL, or set to the external LO input. An attenuator in the RF path provides for gain control over a range of 31 dB in 1 dB steps. Approximately 30 dB of gain is provided by the RF downconverter. Tuner configurations are controlled by digital bits from the FPGA and these signals can be switched rapidly. Typical response times are less than 100 nsec.
The noise diode and 50 ohm terminator can be used for testing and characterization of the down-converter. With assumptions about operating temperature and matching this allows for a crude Y-factor test of receiver noise figure. It is possible to switch the noise diode in and out rapidly but it should be noted that the noise_enable control signal is used to enable and disable the diode power. For rapid switching it is better to leave the diode on and rely on the isolation of the RF switch. The relay switching time is on the order of 4msec on to off or off to on.
The operating level of the external LO input is +12 dBm at the SMA input. This should activate the +10 dBm mixer accounting for the two RF switches which proceed it. Each of those switches has about 1 dB of loss and some additional drive will be needed at higher frequency to overcome line losses on the board.
Coherence Circuit
The coherence circuit takes in an external 10 MHz reference, an external PPS signal, and an external trigger via SMA connectors. These inputs have transient voltage suppressors to prevent the inputs being damaged. The 10 MHz reference is expected to be a +10 dBm sine wave input that is locked to a GPS derived reference source. The PPS signal should be a TTL level gate every second derived from GPS. The trigger is a TTL level input and can be used for different functions depending on the application. A typical function would be changing modes to blank the tuner during an outgoing radar pulse.
The 10 MHz Reference is split to provide the reference clock for the two PLLs and also is converted to a digital signal to provide 100 nsec timing for the FPGA and tuner mode changes. The PPS and trigger are converted directly for use in the FPGA.
Reconfig and Reset Switches
Two front panel switches are provided. The reconfigure switch initiates an FPGA reconfiguration from the EPCS flash memory that contains the FPGA image. The reset switch is used to reset the NIOS II firmware processor and will result in an operating system reboot and a reset of the receiver mode settings. If the PLL was to become non-responsive it might be necessary to power cycle to reset it.
PLL
Synergy microwave phase locked loop modules are used to provide on board local oscillators. These PLLs are capable of tuning between 240 and 760 MHz in 500 kHz steps and use serial programming lines. An external 10 MHz reference input is used to provide a frequency reference for the PLL. The output of the PLL is amplified and an attenuator controlled by the FPGA can be used to vary the LO level. This is useful as there is some variation in LO level as a function of frequency. The spur levels of the PLLs vary somewhat as a function of tuning frequency and it can be advantageous to tune the PLL slightly off in frequency and use the digital receiver to select the correct channel. This can move spurious signals out of a critical band or suppress them entirely.
If the PLL does not tune first check the appropriate 10 MHz reference signal. The PLL tunes by default to 240 MHz which can also be tested to see if it is active at the default setting. The firmware tunes the PLL to 314 MHz by default.
Network and USB Overview
An Ethernet interface is provided by the Davicom DM9000 ethernet chip. This chip provides a 100 Mbit ethernet interface which is sufficient for web based control and status monitoring of the receiver.
The USB interface uses a RS232 to USB converter to provide the Linux console over USB. This chip used is a FT232RL and the device is in general directly recognized by modern Linux and Windows systems.
JTAG and Serial Overview
A JTAG port is provided for use with the Altera USB Blaster to allow programming of the FPGA, EPCS, and Flash memory. It can also act as a console for the Linux operating system during debugging but cannot boot in this mode.
An extra serial port is provided via a pin header. This serial port is a debugging backup in case the USB port has difficulties. The Linux console could be redirected to this port which shows up as /dev/ttyS0.