Projects/IntegratedRadarReceiver/IntegratedRadarReceiver/ReceiverModes

Receiver Modes Overview

The receiver is divided into two tuners each of which consists of a register set and a phase locked loop. The registers set the control signals for the tuner hardware. Two banks of control signals are maintained for each tuner and these signal sets can be selected using a number of Receiver Operating modes on a per tuner basis. Several of the modes rely on the 10 MHz reference and PPS signals being available as these provide coherent mode changes. The external trigger line is also used for several of the modes. The trigger is most useful in active radar applications where blanking is required.

Receiver Modes

Receiver modes are set on a per tuner basis with register sets s0 and set s1 being available for each of tuners A and B. The particular meaning of a mode is determined by the particular register settings. Modes are set using the a_mode and b_mode commands.

• Receiver Mode Name	Receiver Mode Reg Value	Requirements	Description
  Set Low Control State	0x00	none	The tuner is set to the value of the lower control state s0.
  Set High Control State	0x01	none	The tuner is set to the value of the upper control state s1.
  Trigger Asserted	0x02	An external trigger signal.	The tuner is set to the value of the upper control state s1 is set when the trigger is asserted (high). Otherwise the lower control state s0 is set.
  PPS Alternation	0x03	An external PPS signal.	The tuner is set to the value of the upper control state s1 and then the lower state s0 on an alternating basis with each PPS signal.
  Trigger Alternation	0x04	An external trigger signal.	The tuner is set to the value of the upper control state s1 and then the lower state s0 on an alternating basis with each trigger signal.
  Trigger Interval	0x05	An external trigger signal. Interval register is set for the tuner.	The tuner is set to the value of the upper control state s1 starting at the trigger edge for an interval in 100nsec ticks set by the interval register. Actual response time of the analog elements may have latencies.
  PPS Interval	0x06	An external PPS signal. Interval register is set for the tuner.	The tuner is set to the value of the upper control state s1 starting at the trigger edge for an interval in 100nsec ticks set by the interval register. Otherwise state s0 is used. Actual response time of the analog elements may have latencies.
  Trigger Delay	0x07	An external trigger signal. Interval and delay registers are set for the tuner.	The tuner is set to the value of the upper control state s1 starting at the trigger edge plus the value of the delay register in 100 nsec ticks. This mode is maintained for an interval in 100nsec ticks set by the interval register. Otherwise state s0 is used. Actual response time of the analog elements may have latencies.

As a note for delay and interval modes the length of the combined delay and interval must be less than the time period between trigger or PPS signals. In these modes the trigger or PPS signal effectively clear the counter which will asserts the mode or computes the delay.

Receiver Control Registers

The receiver is controlled by a series of registers. These map directly to hardware bits which set the state of the analog elements. The meaning of each register is dependent on the configuration of these elements. These bits may be changed on a rapid timescale by the receiver FPGA but the analog response will often be the limiting factor.

Tuner Mode Registers

• Receiver Register	Tuner Analog Element	Valid Range	Description
  a_mode	tuner A mode	0 to 7	Sets the mode for tuner A.
  b_mode	tuner B mode	0 to 7	Sets the mode for tuner B.
  a_interval	tuner A interval	30 bits	Sets the interval for tuner A in 100 nsec ticks (about 1.78 minutes max, 100 nsec min). Zero will effectively disable the interval mode.
  b_interval	tuner B interval	30 bits	Sets the interval for tuner B in 100 nsec ticks (about 1.78 minutes max, 100 nsec min). Zero will effectively disable the interval mode.
  a_delay	tuner A delay	30 bits	Sets the delay for tuner A in 100 nsec ticks (about 1.78 minutes max, 100 nsec min). Zero will effectively disable the interval mode.
  b_delay	tuner B delay	30 bits	Sets the delay for tuner B in 100 nsec ticks (about 1.78 minutes max, 100 nsec min). Zero will effectively disable the delay mode.

Tuner A state S0

• Receiver Register	Tuner Analog Element	Valid Range	Description
  a_s0_noise_enable	noise diode power	0 or 1	Enables the noise diode power when high.
  a_s0_lo_enable	LO blanking switch	0 or 1	Enables the input to the mixer when high, the mixer input is terminated to 50 ohms when low.
  a_s0_lo_select	LO input switch	0 or 1	Selects the external LO input when high, the internal tuner PLL when low.
  a_s0_rf_path	RF path switch	0 or 1	Selects the RF bypass path for the tuner RF path input when high, the IF chain input when low.
  a_s0_rf_output	RF output switch	0 or 1	Selects the RF bypass path for the tuner RF path output when low, the IF chain output when high.
  a_s0_rf_input	RF input switch	0 to 3	0x7 selects RF input B, 0xB selects RF input A, 0xD selects the noise diode, 0xE selects the 50 ohm terminator. Other states are undefined.
  a_s0_attenuator	RF attenuator	0 to 31	Selects value of the RF attenuator in the IF path. Bits correspond to different attenuator step sizes (0 = 1 dB, 1 = 2 dB, 2 = 4 dB, 3 = 8 dB, 4 = 16 dB) so the value is the attenuation in dB.

Tuner A state S1

• Receiver Register	Tuner Analog Element	Valid Range	Description
  a_s1_noise_enable	noise diode power	0 or 1	Enables the noise diode power when high.
  a_s1_lo_enable	LO blanking switch	0 or 1	Enables the input to the mixer when high, the mixer input is terminated to 50 ohms when low.
  a_s1_lo_select	LO input switch	0 or 1	Selects the external LO input when high, the internal tuner PLL when low.
  a_s1_rf_path	RF path switch	0 or 1	Selects the RF bypass path for the tuner RF path input when high, the IF chain input when low.
  a_s1_rf_output	RF output switch	0 or 1	Selects the RF bypass path for the tuner RF path output when low, the IF chain output when high.
  a_s1_rf_input	RF input switch	0 to 3	0x7 selects RF input B, 0xB selects RF input A, 0xD selects the noise diode, 0xE selects the 50 ohm terminator. Other states are undefined.
  a_s1_attenuator	RF attenuator	0 to 31	Selects value of the RF attenuator in the IF path. Bits correspond to different attenuator step sizes (0 = 1 dB, 1 = 2 dB, 2 = 4 dB, 3 = 8 dB, 4 = 16 dB) so the value is the attenuation in dB.

Tuner B state S0

• Receiver Register	Tuner Analog Element	Valid Range	Description
  b_s0_noise_enable	noise diode power	0 or 1	Enables the noise diode power when high.
  b_s0_lo_enable	LO blanking switch	0 or 1	Enables the input to the mixer when high, the mixer input is terminated to 50 ohms when low.
  b_s0_lo_select	LO input switch	0 or 1	Selects the external LO input when high, the internal tuner PLL when low.
  b_s0_rf_path	RF path switch	0 or 1	Selects the RF bypass path for the tuner RF path input when high, the IF chain input when low.
  b_s0_rf_output	RF output switch	0 or 1	Selects the RF bypass path for the tuner RF path output when low, the IF chain output when high.
  b_s0_rf_input	RF input switch	0 to 3	0x7 selects RF input B, 0xB selects RF input A, 0xD selects the noise diode, 0xE selects the 50 ohm terminator. Other states are undefined.
  b_s0_attenuator	RF attenuator	0 to 31	Selects value of the RF attenuator in the IF path. Bits correspond to different attenuator step sizes (0 = 1 dB, 1 = 2 dB, 2 = 4 dB, 3 = 8 dB, 4 = 16 dB) so the value is the attenuation in dB.

Tuner B state S1

• Receiver Register	Tuner Analog Element	Valid Range	Description
  b_s1_noise_enable	noise diode power	0 or 1	Enables the noise diode power when high.
  b_s1_lo_enable	LO blanking switch	0 or 1	Enables the input to the mixer when high, the mixer input is terminated to 50 ohms when low.
  b_s1_lo_select	LO input switch	0 or 1	Selects the external LO input when high, the internal tuner PLL when low.
  b_s1_rf_path	RF path switch	0 or 1	Selects the RF bypass path for the tuner RF path input when high, the IF chain input when low.
  b_s1_rf_output	RF output switch	0 or 1	Selects the RF bypass path for the tuner RF path output when low, the IF chain output when high.
  b_s1_rf_input	RF input switch	0 to 3	0x7 selects RF input B, 0xB selects RF input A, 0xD selects the noise diode, 0xE selects the 50 ohm terminator. Other states are undefined.
  b_s1_attenuator	RF attenuator	0 to 31	Selects value of the RF attenuator in the IF path. Bits correspond to different attenuator step sizes (0 = 1 dB, 1 = 2 dB, 2 = 4 dB, 3 = 8 dB, 4 = 16 dB) so the value is the attenuation in dB.

Receiver Status Registers

Status registers aren't that meaningful at the moment. The firmware should probably be modified to have these registers provide signal detection capability rather than level detection.

• Receiver Register	Tuner Analog Element	Valid Range	Description
  trigger	external trigger level	0 or 1	High when the external trigger is high. Will not latch periodic triggers unless you get lucky.
  pps	external pps level	0 or 1	High when the external pps is high. Will not latch periodic pps signals unless you get lucky.

PLL Control

The Phase Locked Loops are used to provide a local LO source for the mixer in each tuner. The UHF tuner PLLs are capable of generating between 240 and 760 MHz output in 500 kHz steps. The PLLs are not controlled directly using their enable, clock, and data registers. These are used by the control software to serialize the appropriate tuning commands. The PLL attenuators are used to adjust LO levels. The lock signal indicates the PLL has a valid external 10 MHz reference signal. The error signal indicates an error in lock, tuning, or programming. NOTE : Currently there is a bug in the programming which appears to active the error signal despite proper PLL operation.

Tuner A PLL

• PLL Register	PLL Analog Element	Valid Range	Description
  pll_a_enable	pll enable line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_a_clk	pll clk line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_a_data	pll data line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_a_attenuator	pll output attenuator	0 to 31	Controls the attenuator level at the output of the PLL in 0.5 dB increments. Bits correspond to different attenuator step sizes (0 = 0.5 dB, 1 = 1 dB, 2 = 2 dB, 3 = 4 dB, 4 = 8 dB). Used for adjusting LO input levels into the mixer which can vary as a function of frequency.
  pll_a_lock	pll lock line	0 or 1	Indicates the PLL is locked to an external 10 MHz reference signal.
  pll_a_error	pll error line	0 or 1	Indicates the PLL error status which can be due to lack of lock, out of VCO range, or a programming error. This is currently high after programming due to an unknown problem likely due to software.

Tuner B PLL

• PLL Register	PLL Analog Element	Valid Range	Description
  pll_b_enable	pll enable line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_b_clk	pll clk line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_b_data	pll data line	0 or 1	Used in serial programming of the PLL. Not used at the user level.
  pll_b_attenuator	pll output attenuator	0 to 31	Controls the attenuator level at the output of the PLL in 0.5 dB increments. Bits correspond to different attenuator step sizes (0 = 0.5 dB, 1 = 1 dB, 2 = 2 dB, 3 = 4 dB, 4 = 8 dB). Used for adjusting LO input levels into the mixer which can vary as a function of frequency.
  pll_b_lock	pll lock line	0 or 1	Indicates the PLL is locked to an external 10 MHz reference signal.
  pll_b_error	pll error line	0 or 1	Indicates the PLL error status which can be due to lack of lock, out of VCO range, or a programming error. This is currently high after programming due to an unknown problem likely due to software.