Projects/MidasBeaconReceiver/MidasBeaconReceiver/BeaconTuner

Beacon Tuner

The MIDAS-M Beacon Tuner will be implemented that combines received signals from four center frequencies (150,243,400,1067 MHz) into a single IF at 126 MHz which is suitable for digitization using the existing MIDAS-M Software Radio platform. Digital downconversion will then be used to channelize and select the required beacon monitoring frequencies.

Beacon Tuner Subproject Tasks

Design

• Specify overall design requirements and performance characteristics for the beacon tuner hardware.

• Create an Eagleware model of the receiver signal path in sections. Sections will include an RF front section for each frequency, an upconverter/downconverter section, and a hybrid/filter section for combining the signals.

• Simulate the performance of the sections indvidually and in combination to evaluate gain, noise figure, pass bands, intermodulation, co-channel interference/coupling, and noise performance.

• Vary parts, filters, and stage organization to optimize performance and evaluate potential tradeoffs.

• Create a schematic design of the tuner sections using subsystems from previously implemented MIDAS-M tuners.

Fabrication

• Finalize design, check lead times, and order any needed parts.

• Implement tuner section PCB layout of schematic design. Get design past all design rule checking and DFM steps.

• Design review of PCB layout and final tuner design.

• Send PCB data for fabrication, organize parts for assembler.

• Hand assemble one circuit board while others are externally soldered. Learn about soldering techniques.

Control

• Develop FPGA control firmware from existing MIDAS-M control firmware. Implement particular data and control port mappings. Develop interface software.

• Implement pulsed noise diode tuner test mode.

• Develop web based control software interface for the tuner.

Testing and Integration

• Test assembled board with firmware and evaluate control of all elements of the board hardware (RF, digital, etc).

• Test tuner board using FPGA control, RF signal generation, and network analyzer.

• Test performance of tuner for different input signal levels with different input frequency band combinations (single tone and two tone testing).

• Integrate tuner into reference platform and test using live signals.

• Test tuner board integrated with turnstile antennas and MIDAS-M system for data acquisition.

• Test tuner acquired data with signal processing software.

Design Notes

• A cPCI physical form factor will be used for power and mechanical design.

• The Firefly FPGA running uClinux will be used for control with Ethernet access and serial over USB for a console.

• An up/down conversion architecture will be used to allow the receiver channels to be symmetric in performance characteristics.

• The output IF will be 126 MHz with a pass band optimized for a 72 MHz digitization A/D converter frequency.

• A single noise diode should be injected using directional couplers into all the tuner channels to allow delay and antenna reflection measurements to be made for calibration.

• Calibration of the phase delays through the different channels is an issue. We may wish to include a phase shifting element in each channel under digital control

  • to allow us to offset the different channels to zero delay in analog. If we can come up with an in the field measurement scheme this would allow us to maintain the receiver phase offsets adaptively. It might actually be easier than doing it in the signal processing...

Interference Summary (under construction)

Overall Summary: